• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention aims to solve the problem of a high photomask and a low precision because the drawing time of the circuit pattern is remarkably long when there is an oblique line in the circuit pattern. On the light shielding pattern 3b formed on one main surface of the transparent substrate 2 based on the layout data of the polygonal circuit pattern including the inclined line, the inclined line is the width W of the inclined line and the resolution of the projection exposure apparatus. (Rp) an inclination line converted from the transfer magnification m of the projection exposure apparatus to polygonal data represented by a step shape by Np rectangles defined by Np = int (W / Rp / m) + 1 It is formed on one main surface of the transparent substrate 2 based on the layout data of the circuit pattern of the polygon contained.
    公开号:KR20000057825A
    申请号:KR1020000004268
    申请日:2000-01-28
    公开日:2000-09-25
    发明作者:가몬가즈야
    申请人:다니구찌 이찌로오, 기타오카 다카시；미쓰비시덴키 가부시키가이샤；
    IPC主号:
    专利说明:

    Photomask, manufacturing method of photomask, inspection and correction method of photomask and usage method of photomask {PHOTOMASK, METHOD OF MANUFACTURE, METHOD OF TEST / REPAIR, AND METHOD OF USE THEREFOR}
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to photomasks used in the manufacturing process of semiconductor integrated circuit devices and liquid crystal displays, and methods of manufacturing the photomasks, inspection and modification methods, and methods of use.
    In recent years, the manufacture of a photomask using the variable beam vector scanning electron beam exposure apparatus is increasing.
    It is a block diagram which shows the electron beam exposure apparatus of a variable shaping beam vector scan type | mold. In Fig. 13, reference numeral 101 denotes an electron beam exposure apparatus of a variable beamforming vector scan type, reference numeral 100 denotes a LaB 6 electron gun, reference numeral 103 denotes a first molding aperture, reference numeral 104 denotes a first molded lens, Reference numeral 105 denotes a first molded deflector, reference numeral 106 denotes a second molded lens, reference numeral 107 denotes a second molded aperture, reference numeral 108 denotes a reduction lens, reference numeral 109 denotes a blanking electrode, reference numeral 110 denotes a The deflector, 111 is a focusing lens, and 112 is a drawing field.
    Reference numeral 113 denotes a first shaping aperture 103, a first shaping lens 104, a first shaping deflector 105, a second shaping lens 106, and a second shaping aperture ( 107, and a reference numeral 114 denotes a converging deflection lens portion comprising a deflector 110 and a focusing lens 111. As shown in FIG. Reference numeral 115 denotes a photomask as an object to be exposed placed on a stage (not shown).
    In the variable beam vector scan type electron beam exposure apparatus 101, when drawing a circuit pattern, layout data of the circuit pattern is divided into simple rectangles as shown in FIG. The exposure method is adopted. Therefore, in the electron beam exposure apparatus 101 of the variable shaping beam vector scan type, when the layout of the circuit pattern is simple, compared with the case where the layout of the circuit pattern is complicated, the number of rectangles to be exposed even though the area to be exposed is the same is small. ) Is high.
    In addition, as shown in FIG. 14B, the variable beam vector scan type electron beam exposure apparatus 101 scans an entire photomask including a portion exposed and unexposed with a Gaussian beam to scan a circuit pattern. Gaussian beam raster scanning type electron beam exposure apparatus employing a drawing method, or Gaussian employing a method of drawing a circuit pattern by scanning only the exposed portion with a Gaussian beam as shown in Fig. 14C. Compared with the electron beam exposure apparatus of the beam vector scan type, the throughput is excellent in that the throughput is high.
    In recent years, in order to fill a small area with a complicated function due to high integration of LSI, wires extending in the inclined direction have been increasing because the degree of freedom is small only by the wires extending vertically and horizontally.
    However, in the electron beam exposure apparatus 101 of the variable shaping beam vector scan type, the first and second shaping portions are not configured to be capable of drawing inclined lines. Therefore, in the case of drawing a polygonal circuit pattern including an inclination line in the variable beam vector scan type electron beam exposure apparatus 101, first, as shown in FIG. 14A, a polygonal circuit pattern including an inclination line is shown. The layout data is converted into polygonal data in which the oblique line is represented in a step shape by a plurality of elongated rectangles having a width equal to the resolution of the electron beam exposure apparatus 101, and the whole is composed of a plurality of rectangles. That is, the width W of the inclined line is designed to be an integer multiple of the resolution Rw of the electron beam exposure apparatus 101, and the layout data of the polygonal circuit pattern including the inclined line is defined at Nw = W / Rw. It is converted into polygonal data represented by a step shape by the Nw rectangles to be formed and the whole consists of a plurality of rectangles. Then, by exposing these rectangles one by one, a circuit pattern of a polygon including an oblique line is drawn.
    When the layout data is uniformly shrunk, the rectangular layout data is precisely placed on the grid, but in the case of polygonal layout data including oblique lines, the layout data is accurately loaded on the grid. Can not. If the layout data after the shrink is not accurately loaded on the grid, a rounding error occurs in the layout data, and drawing accuracy deteriorates.
    15 is a configuration diagram showing a projection exposure apparatus for manufacturing a semiconductor integrated circuit or a liquid crystal display using a photomask manufactured using an electron beam exposure apparatus. In Fig. 15, reference numeral 201 denotes a projection exposure apparatus, reference numeral 202 denotes an Hg lamp as a light source, reference numeral 203 denotes a first lens, reference numeral 204 denotes a first mirror, reference numeral 205 denotes a second lens, reference numeral 206 Fly-eye lens, reference numeral 207 denotes a secondary light source, reference numeral 208 denotes a third lens, reference numeral 209 denotes a blind lens, reference numeral 210 denotes a fourth lens, reference numeral 211 denotes a second mirror, and reference numeral 212 denotes a fifth lens. Reference numeral 213 denotes a sixth lens, reference numeral 214 is coplanar, and reference numeral 215 is a seventh lens.
    Reference numeral 216 denotes a photomask, reference numeral 217 denotes a wafer to be exposed, reference numeral 218 denotes light emitted from the Hg lamp 202, reference numeral 219 denotes diffracted light diffracted by the photomask 216.
    The resolution Rp of the projection exposure apparatus 201 is defined as Rp = k1 · λ / NA using the exposure wavelength λ, the numerical aperture NA of the lens, and the process constant k1. For this reason, when the width of the light shielding pattern formed on one main surface of the photomask 216 is m · Rp or less, the shape of the light shielding pattern cannot be accurately represented on the wafer 217 as the object to be exposed, and the outline is rounded. do. For example, FIG. 16A illustrates a wafer in which a photomask having a light shielding pattern having a square hole having one side of m · Rp or less is mounted on the projection exposure apparatus shown in FIG. 15 to expose the wafer 217. On 217, the shape of the light shielding pattern is represented by the shape shown in FIG. 16B.
    When the inclined line is drawn using the variable beam vector scan type electron beam exposure apparatus, as described above, if there is an inclined line in the circuit pattern, the drawing time of the circuit pattern is remarkably long, and thus the throughput of the electron beam exposure apparatus. This deterioration has caused problems such as a rise in the price of the photomask.
    In addition, when the drawing time is long, the influence of the drift of the stage of the electron beam exposure apparatus also increases, so that there is a problem that the length dimension error is enlarged and the precision of the photomask is lowered.
    This invention is made | formed in order to solve the above-mentioned subject, and an object of this invention is to obtain a highly accurate photomask at low cost.
    Moreover, it aims at obtaining the manufacturing method of a photomask, the inspection correction method, and a usage method.
    1 is a block diagram showing a photomask according to a first embodiment of the present invention,
    2 is a flowchart showing a method of manufacturing a photomask;
    3 is a view for explaining a third embodiment;
    4 is a view for explaining a fourth embodiment;
    5 is a view for explaining a fifth embodiment;
    6 is a view for explaining a sixth embodiment;
    7 is a view for explaining a seventh embodiment;
    8 is a view for explaining an eighth embodiment;
    9 is a view for explaining a ninth embodiment;
    10 is a view for explaining a tenth embodiment;
    11 is a view for explaining a defect correction method of a photomask,
    12 is a view for explaining a method of using a photomask,
    13 is a configuration diagram showing an electron beam exposure apparatus of a variable shaping beam vector scan type;
    14 is a view for explaining an exposure method of an electron beam exposure apparatus;
    15 is a configuration diagram showing a projection exposure apparatus;
    16 is a diagram for explaining a projection exposure apparatus.
    Explanation of symbols for the main parts of the drawings
    1: photomask 2: transparent substrate
    3b: Shading pattern 4: Line equivalent to inclined line
    4a, 4b: positions corresponding to the ends of the inclined line
    4c: midpoint of the line corresponding to the oblique line
    4d: vertical bisector of the line corresponding to the inclined line
    5: circuit pattern of polygon including slope line
    6: inclined line 6a, 6b: end of the inclined line
    7a, 7b: side connected to the end of the inclined line
    8a, 8b: sides connected to positions corresponding to the ends of the inclined lines
    9: micro rectangle
    The photomask according to the present invention includes a transparent substrate and a light shielding pattern in which a polygonal circuit pattern including an inclined line is represented as a polygon in which the inclined line is represented in a step shape by a plurality of rectangles. And Rw < R < Rp · m, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus.
    According to the present invention, it is possible to provide a photomask in which the area of the polygon including the inclined line is equal to the area of the polygon in which the inclined line is represented by the step shape.
    According to the present invention, a port in which the side connected to the end of the inclined line in the polygon including the inclined line and the side connected to the position corresponding to the end of the inclined line in the polygon in which the inclined line is stepped are in parallel relationship. You can also provide a mask.
    According to the present invention, a port in which a side connected to an end of an inclined line in a polygon including an inclined line and a side connected to a position corresponding to an end of the inclined line in a polygon in which the inclined line is represented by a step shape have a right angle relationship. You can also provide a mask.
    According to the present invention, when a side connected to an end of an inclined line in a polygon including an inclined line is in parallel relationship with each other, a step of providing a photomask in which the stepped shape representing the inclined line is point symmetric with respect to the midpoint of the line corresponding to the inclined line You may.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are parallel to each other, the stepped shape representing the inclined line is mirror-symmetrical with respect to the vertical bisector of the line corresponding to the inclined line. May be provided.
    According to the present invention, when a side connected to an end of an inclined line in a polygon including an inclined line is perpendicular to each other, a stepped shape representing the inclined line is point-symmetrical with respect to the midpoint of a line corresponding to the inclined line. You may.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are perpendicular to each other, the stepped shape representing the inclined line is mirror-symmetric with respect to the vertical bisector of the line corresponding to the inclined line. May be provided.
    In the method of manufacturing a photomask according to the present invention, a step of laying out a circuit pattern and creating the layout data, and the layout data of a polygonal circuit pattern including an inclined line, the inclined lines are represented in steps by a plurality of rectangles. Converting the polygon into data of a polygon consisting of a plurality of rectangles; and drawing a circuit pattern based on layout data after conversion of the circuit pattern of the polygon including the oblique line, and including the oblique line In the process of converting the layout data, the width R of the rectangle representing the oblique line is in the range of Rw < R < Rp · m, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, Rw is the resolution of the mask drawing device).
    According to the present invention, when there are a plurality of methods for converting layout data of a polygonal circuit pattern including an inclined line, a method of manufacturing a photomask can be provided in which a method for selecting all rectangles is small.
    According to the present invention, when there are a plurality of methods for converting layout data of a polygonal circuit pattern including an inclined line, a method of manufacturing a photomask can be provided in which a method with a small number of micro rectangles is selected.
    According to the present invention, when there are a plurality of methods for converting layout data of a circuit pattern of a polygon including an oblique line, a method of manufacturing a photomask is provided in which a method of selecting a method in which the micro rectangle is not located at the outer periphery of the polygon consisting of a plurality of rectangles is selected. You can also provide
    The inspection and correction method of the photomask according to the present invention includes a transparent substrate and a light shielding pattern in which a polygonal circuit pattern including an inclined line is represented as a polygon in which the inclined line is represented by a plurality of rectangles in a stepped shape, the width of the rectangle (R) inspects and corrects the defect occurring at the position of the line corresponding to the inclination line of the photomask in the range of Rw <R <Rp · m at an angle with reference to the layout data of the circuit pattern. , m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, Rw is the resolution of the mask drawing apparatus.
    A method of using a photomask according to the present invention includes a transparent substrate and a light shielding pattern in which a polygonal circuit pattern including an inclined line is represented as a polygon in which the inclined line is represented by a step shape by a plurality of rectangles, and the width of the rectangle ( R) manufactures a semiconductor integrated circuit using a photomask in a range of Rw < R < Rp · m, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the mask drawing apparatus. Resolution).
    A method of using a photomask according to the present invention comprises a transparent substrate and a light shielding pattern in which a polygonal circuit pattern including an inclined line is represented as a polygon in which the inclined line is represented in a step shape by a plurality of rectangles, and the width of the rectangle ( R) manufactures a liquid crystal display using a photomask in the range of Rw < R < Rp · m, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the mask drawing apparatus. definition).
    Hereinafter, an embodiment of the present invention will be described.
    (Example 1)
    1 is a block diagram showing a photomask according to a first embodiment of the present invention. In Fig. 1, reference numeral 1 denotes a photomask, reference numeral 2 denotes a transparent substrate, and reference numeral 3a denotes an electron beam exposure of a variable shaping beam vector scan type based on layout data of a rectangular circuit pattern having no oblique lines. The light shielding pattern formed on one main surface of the transparent substrate 2 by exposure by a device (mask drawing device), reference numeral 3b, is a variable beam beam vector scan based on layout data of a polygonal circuit pattern including an inclination line It is a light shielding pattern formed on one main surface of the transparent substrate 2 by exposing with a type electron beam exposure apparatus. Reference numeral 4 denotes a line corresponding to the inclined line in the circuit pattern of the polygon including the inclined line.
    The light shielding pattern 3b has Np = int from the width W of the oblique line, the resolution Rp of the projection exposure apparatus (exposure apparatus) to which the photomask 1 is mounted, and the transfer magnification m of the projection exposure apparatus. One of the transparent substrates 2 is based on the layout data of the circuit pattern of the polygon including the oblique line, which is converted into the polygonal data represented by the step shape by Np rectangles defined as (W / Rp / m) +1. It is formed on the main surface.
    Here, in general, since Rp · m is 10 times or more larger than the resolution Rw of the electron beam exposure apparatus, Np is smaller than Nw. As a result, the rectangular width R is larger than the resolution Rw of the electron beam exposure apparatus. . It is also apparent that the width R of the rectangle is smaller than Rp · m from Np = int (W / Rp / m) +1. In other words, the width R of the rectangle is in the range of Rw < R <
    In other words, the light shielding pattern 3b represents a circuit pattern of a polygon including an inclined line as a polygon in which the inclined line is represented in a step shape by a plurality of rectangles, and the width R of the rectangle is Rw <R <Rp. It is in the range of m.
    FIG. 1 shows, as an example, that the inclined line in a polygonal circuit pattern including an inclined line includes a rectangle 4x having a width R1 of Rw <R1 <Rp · m and a width R2 of Rw <R2 <Rp ·. The example shown by step shape by the rectangle 4y which is the range of m is shown.
    As described above, according to the first embodiment, the light shielding pattern 3b is formed of the circuit pattern of the polygon including the oblique line, in which the oblique line is converted into the polygonal data represented by the stepped shape by Np (<Nm) rectangles. Since it is formed based on the layout data, the circuit pattern is drawn in a short time with fewer exposure times as compared with the conventional case. As a result, the throughput of an electron beam exposure apparatus improves and the photomask becomes low cost. Moreover, the influence of the drift of an electron beam exposure apparatus becomes small, and the effect that a photomask becomes high precision with a small length dimension error can also be acquired.
    (Example 2)
    In Example 2, the manufacturing method of the photomask described in Example 1 is demonstrated. 2 is a flowchart showing a method of manufacturing a photomask. When manufacturing the photomask, first, the circuit pattern required for the device to be manufactured is laid out using CAD (step ST1).
    Thereafter, in order to improve the degree of integration of the circuit pattern, the circuit pattern is densified and layout data of the circuit pattern is created (step ST2). At this time, in order to bend the wiring appropriately while integrating more circuit patterns in a small area while keeping the design rule, not only the wiring extending in the longitudinal direction but also the wiring extending in the inclined direction may be used.
    After that, the layout data of the circuit pattern is converted into a standard format (step ST3).
    Thereafter, data for each layer is extracted and expanded from the layout data of the circuit pattern (step ST4).
    Thereafter, an area for converting graphics in the layout data of the circuit pattern is designated (step ST5).
    Thereafter, the repeating portion and the non-repeating portion in the layout data of the circuit pattern are once divided (step ST6).
    Thereafter, the repeating portion and the non-repeating portion are divided into small segments (step ST7). However, division of the repeating part is performed when the repeating part is larger than the segment.
    Thereafter, for each segment, existing graphics operations such as deduplication and the like are processed (step ST8).
    Thereafter, the layout data of the circuit pattern of the polygon including the inclined line is the width of the rectangle representing the inclined line in the polygonal data in which the inclined line is represented in a step shape by a plurality of rectangles and the whole consists of a plurality of rectangles. (R) is converted to the range of Rw < R < Rp · m (step ST9). In other words, the layout data of the circuit pattern of the polygon including the inclined line is defined as Np = int (W /) from the width W of the inclined line, the resolution Rp of the projection exposure apparatus, and the transfer magnification m of the projection exposure apparatus. Np rectangles defined by Rp / m) +1 are converted into data of a polygon represented by a stepped shape.
    Thereafter, the repeating portion is assigned to the non-repeatable portion (step ST10).
    Thereafter, conversion is made to the format of the variable beamforming electron beam exposure apparatus using the layout data of the circuit pattern (step ST11).
    Then, the circuit pattern is drawn by the variable beamforming electron beam exposure apparatus based on the layout data of the circuit pattern having the layout data after the conversion of the polygonal circuit pattern including the oblique line (step ST12). That is, since the entire layout data after the conversion of the circuit pattern of the polygon including the oblique line is made up of a plurality of rectangles, the circuit patterns are drawn by exposing these rectangles one by one by the variable beam scanning electron beam exposure apparatus. .
    As described above, according to the second embodiment, the layout data of the circuit pattern of the polygon including the inclined line includes the width W of the inclined line, the resolution power Rp of the projection exposure apparatus, and the transfer magnification (m) of the projection exposure apparatus. ) Is converted into data of a polygon represented by a step shape by Np rectangles defined by Np = int (W / Rp / m) + 1, so that the number of exposures is smaller than in the conventional case, and the circuit pattern is drawn. Short time As a result, the throughput of an electron beam exposure apparatus improves and the effect which can manufacture a low cost photomask can be acquired. In addition, the effect of the drift of the electron beam exposure apparatus is reduced, and a high-precision photomask with a small length dimension error can be obtained.
    (Example 3)
    In Embodiments 3 to 6, examples of light-shielding patterns formed on the basis of layout data of polygonal circuit patterns including oblique lines will be described.
    3 is a diagram for explaining a third embodiment. FIG. 3A illustrates a polygonal circuit pattern 5 including an inclination line, and FIGS. 3B to 3G illustrate a polygonal circuit including an inclination line shown in FIG. 3A. The light-shielding pattern 3b formed on the basis of the layout data after the conversion of the pattern 5, that is, the circuit pattern 5 of the polygon including the inclination line shown in Fig. 3 (a), the inclination line is formed by a plurality of rectangles. In the light shielding pattern 3b shown as a polygon shown in a step shape, it is shown that the width R of the rectangle representing the inclined line is in the range of Rw < R <
    3 (b) and 3 (e) show the cases where the width W of the inclined line 6 in the circuit pattern 5 shown in FIG. 3 (a) is smaller than Rp · m. 3 (c), 3 (d), 3 (f) and 3 (g) show the inclination lines 6 in the circuit pattern 5 shown in Fig. 3 (a). The case where the width W is larger than Rp · m is shown.
    The side 7a and the side 7b which are connected to the edge part of the inclination line in the circuit pattern 5 shown to Fig.3 (a) are in parallel relationship with each other. The area of the light shielding pattern 3b shown in Figs. 3B to 3G is the same as the area of the circuit pattern 5 shown in Fig. 3A. In the light shielding pattern 3b shown in FIGS. 3B to 3G, the position 4a corresponding to the end of the inclined line and the stepped shape connecting the position 4b are the midpoints of the lines corresponding to the inclined line. It is point symmetric with respect to (4c). That is, in the light shielding pattern 3b shown in Figs. 3B to 3G, the side 7a and the side 7b connected to the end of the inclined line shown in Fig. 3A are parallel to each other. On the basis of the layout data after converting the inclined line into a step symmetrical step symmetric with respect to the midpoint 4c of the line corresponding to the inclined line while maintaining the area before and after the conversion of the layout data of the circuit pattern 5 The formed light shielding pattern 3b is shown. Further, the slope line is a step symmetrical step with respect to the midpoint of the line corresponding to the inclined line, while maintaining the area before and after the conversion of the layout data of the circuit pattern in which the two sides connected to the ends of the inclined line are parallel to each other. In the method of conversion into a shape, the symmetry of the conversion portion is secured.
    In addition, the edges 8a and 8b connected to positions 4a and 4b corresponding to the end portions of the inclined line in the light shielding pattern 3b shown in Figs. Light blocking pattern 3b shown in FIGS. 3E to 3G in parallel with the sides 7a and 7b connected to the ends of the inclined lines in the circuit pattern 5 shown in a). The sides 8a and 8b connected to the positions 4a and 4b corresponding to the end portions of the inclined line in FIG. 3 are connected to the ends of the inclined line 6 in the circuit pattern 5 shown in FIG. It is perpendicular to the sides 7a and 7b. The sides 8a and 8b form an acute angle with the line 4 corresponding to the inclined line. (B) of FIG. 3 is proportional to (e) of FIG. 3, (c) of FIG. 3 is proportional to (f) of FIG. 3, and (d) of FIG. 3 is proportional to (g) of FIG. Since the number of bends in the step shape is small, it is excellent in that the amount of data after conversion is small.
    (Example 4)
    4 is a view for explaining a fourth embodiment. 4A illustrates a polygonal circuit pattern 5 including an inclination line, and FIGS. 4B to 4G illustrate a polygonal circuit including an inclination line shown in FIG. 4A. The light-shielding pattern 3b formed on the basis of the layout data after the conversion of the pattern 5, that is, the circuit pattern 5 of the polygon including the inclination line shown in Fig. 4A, is made up of a plurality of rectangles. In the light shielding pattern 3b shown as a polygon shown in a step shape, it is shown that the width R of the rectangle representing the inclined line is in the range of Rw < R <
    4B and 4E show the cases where the width W of the inclined line 6 in the circuit pattern 5 shown in FIG. 4A is smaller than Rp · m. 4 (c), 4 (d), 4 (f) and 4 (g) show the inclination lines 6 in the circuit pattern 5 shown in Fig. 4 (a). The case where width W is larger than Rp * m is shown.
    The side 7a and the side 7b which are connected to the edge part of the inclination line in the circuit pattern 5 shown to Fig.4 (a) are in parallel relationship with each other. The area of the light shielding pattern 3b shown to FIG. 4B-FIG. 4G is the same as the area of the circuit pattern 5 shown to FIG. 4A. The position 4a corresponding to the end of the inclined line in the light shielding pattern 3b shown in FIGS. 4B to 4G and the stepped shape connecting the position 4b are perpendicular to the line corresponding to the inclined line. It is mirror symmetry with respect to the bisector 4d. That is, in the light shielding pattern 3b shown in Figs. 4B to 4G, the side 7a and the side 7b connected to the end of the inclined line shown in Fig. 4A are parallel to each other. Layout data after converting the inclined line into a mirror symmetrical step with respect to the vertical bisector 4d of the line corresponding to the inclined line, while maintaining the layout data of the circuit pattern 5 in FIG. The light shielding pattern 3b formed based on this is shown.
    In addition, the side 8a connected to the position 4a corresponding to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 4B-FIG. 4D is shown to FIG. 4A. At the end of the inclined line in the light shielding pattern 3b shown in FIGS. 4B to 4D in parallel with the sides 7a and 7b connected to the end of the inclined line in the circuit pattern 5. The side 8b connected to the corresponding position 4b is at right angles to the side 7a, 7b connected to the end of the inclined line in the circuit pattern 5 shown in Fig. 4A. The side 8a which connects to the position 4a corresponding to the edge part of the inclination line in the light shielding pattern 3b shown to Fig.4 (e)-(g) is the circuit pattern 5 shown to Fig.4 (a). At the end of the inclined line in the light shielding pattern 3b shown in Figs. 4E to 4G, which is perpendicular to the sides 7a and 7b connected to the end of the inclined line 6 in Figs. The side 8b which connects to the corresponding position 4b is Sides (7a, 7b) for connecting to an end of the oblique line 6 in the circuit pattern 5 shown in FIG. 4 (a) and is parallel to the relationship. The sides 8a and 8b form an acute angle with the line 4 corresponding to the inclined line.
    (Example 5)
    5 is a diagram for explaining a fifth embodiment. 5A illustrates a polygonal circuit pattern 5 including an inclination line, and FIGS. 5B to 5G illustrate a polygonal circuit including an inclination line shown in FIG. 5A. The light shielding pattern 3b formed on the basis of the layout data after the conversion of the pattern 5, that is, the circuit pattern 5 of the polygon including the inclination line shown in Fig. 5 (a), the inclination line is formed by a plurality of rectangles. It is the light-shielding pattern 3b shown as the polygon shown by step shape, and has shown that the width | variety R of the rectangle which shows a gradient line is in the range of Rw <R <Rp * m.
    5B and 5E show the cases where the width W of the inclined line 6 in the circuit pattern 5 shown in FIG. 5A is smaller than Rp · m. 5 (c), 5 (d), 5 (f) and 5 (g) show the inclination lines 6 in the circuit pattern 5 shown in Fig. 5 (a). The case where width W is larger than Rp * m is shown.
    The side 7a and the side 7b which are connected to the edge part of the inclined line in the circuit pattern 5 shown to Fig.5 (a) are mutually perpendicular. The area of the light shielding pattern 3b shown in Figs. 5B to 5G is the same as the area of the circuit pattern 5 shown in Fig. 5A. In the light shielding pattern 3b shown in FIGS. 5B to 5G, the position 4a corresponding to the end of the inclined line and the stepped shape connecting the position 4b are the midpoints of the lines corresponding to the inclined line. It is point symmetric with respect to (4c). That is, in the light shielding pattern 3b shown in Figs. 5A to 5G, the sides 7a and 7b connected to the ends of the inclined lines shown in Fig. 5A are perpendicular to each other. Formed on the basis of the layout data after converting the inclined line into a step symmetrical step symmetrical with respect to the midpoint 4c of the line corresponding to the inclined line while maintaining the area before and after the conversion of the layout data of the circuit pattern 5 The light shielding pattern 3b is shown.
    In addition, the side 8a connected to the position 4a corresponding to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 5B-FIG. 5D is shown to FIG. 5A. It is parallel to the side 7a connected to the edge part of the inclination line in the circuit pattern 5, and corresponds to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 5 (b)-FIG. 5 (d). The side 8b connected to the position 4b to be made is in a right angle relationship with the side 7b connected to the end of the inclined line in the circuit pattern 5 shown in FIG. 5A to 5C, which are connected to the position 4a corresponding to the end of the inclined line in the light shielding pattern 3b shown in FIG. 5G, are shown in FIG. A position perpendicular to the side 7a connected to the end of the inclined line 6 of the position corresponding to the end of the inclined line in the light shielding pattern 3b shown in FIGS. 5E to 5G. The side 8b which connects to 4b) is FIG. It is in parallel with the side 7b connected to the edge part of the inclination line 6 in the circuit pattern 5 shown to (a). The sides 8a and 8b form an acute angle with the line 4 corresponding to the inclined line.
    (Example 6)
    6 is a diagram for explaining a sixth embodiment. FIG. 6A illustrates a polygonal circuit pattern 5 including an inclination line, and FIGS. 6B to 6G illustrate a polygonal circuit pattern including an inclination line shown in FIG. 6A. In the light-shielding pattern 3b formed on the basis of the layout data after the conversion of (5), that is, the circuit pattern 5 of the polygon including the inclination line shown in Fig. 6A, the inclination line is stepped by a plurality of rectangles. As the light shielding pattern 3b shown as a polygon represented by the shape, it is shown that the width R of the rectangle representing the oblique line is in the range of Rw < R <
    6B and 6E show the cases where the width W of the inclined line 6 in the circuit pattern 5 shown in FIG. 6A is smaller than Rp · m. 6 (c), 6 (d), 6 (f) and 6 (g) are inclined lines 6 in the circuit pattern 5 shown in Fig. 6 (a). The case where the width W is larger than Rp · m is shown.
    The side 7a and the side 7b which are connected to the edge part of the inclination line in the circuit pattern 5 shown to Fig.6 (a) are mutually perpendicular. The area of the light shielding pattern 3b shown to FIG. 6B-FIG. 6G is the same as the area of the circuit pattern 5 shown to FIG. 6A. In the light shielding pattern 3b shown in FIGS. 6B to 6G, the position 4a corresponding to the end of the inclined line and the stepped shape connecting the position 4b are perpendicular to the line corresponding to the inclined line. It is mirror symmetry with respect to the bisector 4d. That is, in the light shielding pattern 3b shown in Figs. 6B to 6G, the sides 7a and 7b connected to the ends of the inclined lines shown in Fig. 6A are perpendicular to each other. Layout data after converting the inclined line into a mirror symmetrical step with respect to the vertical bisector 4d of the line corresponding to the inclined line while maintaining the layout data of the circuit pattern 5 in The light shielding pattern 3b formed based on this is shown. In addition, while the layout data of the circuit pattern in which the two sides connected to the end of the inclined line are perpendicular to each other is maintained, the inclined line is mirror-symmetrical with respect to the vertical bisector of the line corresponding to the inclined line while maintaining the area before and after conversion. In the method of converting to a stepped shape, the symmetry of the transformed portion is secured.
    In addition, the side 8a connected to the position 4a corresponding to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 6B-FIG. 6D is shown to FIG. 6A. It is parallel to the side 7a connected to the edge part of the inclination line in the circuit pattern 5, and corresponds to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 6 (b)-FIG. 6 (d). The side 8b connected to the position 4b to be made is in parallel with the side 7b connected to the end of the inclined line in the circuit pattern 5 shown in FIG. 6A, and FIG. 6E. The side 8a connected to the position 4a corresponding to the edge part of the inclination line in the light shielding pattern 3b shown to FIG. 6G is the circuit pattern 5 shown to FIG. 6A. A position corresponding to the end of the inclined line in the light shielding pattern 3b shown in FIGS. 6E to 6G, which is perpendicular to the side 7a connected to the end of the inclined line 6 ( The side 8b which connects to 4b) is FIG. It has a right angle relationship with the side 7b connected to the edge part of the inclination line in the circuit pattern 5 shown to (a). The sides 8a and 8b form an acute angle with the line 4 corresponding to the inclined line. (B) of FIG. 6 is proportional to (e) of FIG. 6, (c) of FIG. 6 is proportional to (f) of FIG. 6, and (d) of FIG. 6 is proportional to (g) of FIG. Since the number of bends in the step shape is small, it is excellent in that the amount of data after conversion is small.
    (Example 7)
    In Embodiments 7 to 10, examples of layout data after conversion of polygonal circuit patterns including oblique lines will be described.
    7 is a diagram for explaining a seventh embodiment. 7 (a) to 7 (h) show layout data after the conversion of the polygonal circuit pattern 5 including the oblique line shown in FIG. 3 (a). The layout data after the conversion of the circuit pattern 5 of the polygon including the inclined line shown in Fig. 3A is a polygonal data represented by a plurality of rectangles in a step shape and composed entirely of a plurality of rectangles. Although the width | variety R of the rectangle which shows is the range of Rw <R <Rp * m, in FIG.7 (a)-FIG.7 (h), only the shape which the whole consists of several rectangle is shown.
    The layout data shown in Fig. 7A serves as a basis for forming the light shielding pattern 3b shown in Fig. 3B, and the layout data shown in Fig. 7B is shown in Fig. 3C. It becomes the basis for forming the light shielding pattern 3b shown in FIG. 7, and the layout data shown in FIGS. 7C and 7D form the light shielding pattern 3B shown in FIG. 3D. The layout data shown in (e) of FIG. 7 serves as the basis for forming the light shielding pattern 3b shown in FIG. 3 (e), and the layout data shown in FIG. It becomes the basis for forming the light shielding pattern 3b shown in FIG.3 (f), The layout data shown in FIG.7 (g) and FIG.7 (h) is the light shielding pattern shown in FIG.3 (g). It becomes the basis for forming (3b).
    In general, a small rectangle has poor drawing precision compared to a large rectangle. In addition, when a small rectangle is located in the outer periphery of a polygon, the whole drawing precision which contained the small rectangle will become bad. The smaller the number of rectangles, the smaller the amount of data after conversion.
    When the layout data shown in Fig. 7C and the layout data shown in Fig. 7D are compared, the number of rectangles constituting the layout data shown in Fig. 7C and Fig. 7D are shown. Although the number of the rectangles which constitute the layout data shown is the same, the number of the micro rectangles 9 in the layout data shown in FIG. 7C is the number of the micro rectangles 9 in the layout data shown in FIG. 7D. In addition, the microrectangles 9 constituting the layout data shown in FIG. 7C are located in the outer peripheral portion. Therefore, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 7D, a light shielding pattern having high precision is formed as compared with the case in which the light shielding pattern is formed based on the layout data shown in FIG. 7C. Can be formed. Similarly, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 7H, a light shielding pattern having high precision is formed as compared with the case in which the light shielding pattern is formed based on the layout data shown in FIG. 7G. Can be formed. In particular, since the micro rectangle 9 in the layout data shown in FIG. 7G is smaller than the micro rectangle 9 in the layout data shown in FIG. 7C and is located outside, the micro rectangle 9 in FIG. In the comparison between g) and FIG. 7H, this effect is remarkable.
    (Example 8)
    8 is a diagram for explaining an eighth embodiment. 8A to 8H show layout data after conversion of the circuit pattern 5 of the polygon including the inclined line shown in FIG. 4A. The layout data after conversion of the circuit pattern 5 of the polygon including the inclined line shown in Fig. 4A is represented by a plurality of rectangles in a stepped shape, and is a polygon data composed of a plurality of rectangles as a whole. Although the width R of the rectangle representing the line is in the range of Rw <R <Rp · m, in Figs. 8A to 8H, only the shape of the entire rectangle is shown.
    The layout data shown in FIG. 8A serves as a basis for forming the light shielding pattern 3b shown in FIG. 4B, and the layout data shown in FIG. 8B is shown in FIG. 4C. It is a basic for forming the light shielding pattern 3b shown in FIG. 8, and the layout data shown in FIGS. 8C and 8D form the light shielding pattern 3b shown in FIG. The layout data shown in (e) of FIG. 8 is the basis for forming the light shielding pattern 3b shown in (e) of FIG. 4, and the layout data shown in (f) of FIG. It serves as a basis for forming the light shielding pattern 3b shown in (f) of FIG. 4, and the layout data shown in FIG. 8 (g) and FIG. 8 (h) includes the light shielding pattern ( It is the basis for forming 3b).
    When the layout data shown in Fig. 8C and the layout data shown in Fig. 8D are compared, the number of rectangles constituting the layout data shown in Fig. 8C and the layout shown in Fig. 8D are shown. Although the number of rectangles constituting the data is the same, the number of the micro rectangles 9 in the layout data shown in FIG. 8C is greater than the number of the micro rectangles 9 in the layout data shown in FIG. 8D. In addition, the microrectangles 9 constituting the layout data shown in FIG. 8C are located in the outer peripheral portion. Therefore, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 8 (d), a light shielding pattern having high precision is formed as compared with the case in which the light shielding pattern is formed based on the layout data shown in FIG. 8 (c). Can be formed. Similarly, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 8 (h), the light shielding pattern having high precision is higher than in the case of forming the light shielding pattern based on the layout data shown in FIG. Can be formed. In particular, since the micro rectangle 9 in the layout data shown in FIG. 8G is smaller than the micro rectangle 9 in the layout data shown in FIG. 8C and is located outside, the micro rectangle 9 in FIG. In the comparison between g) and FIG. 8H, this effect is remarkable.
    (Example 9)
    9 is a diagram for explaining a ninth embodiment. 9 (a) to 9 (h) show layout data after conversion of the circuit pattern 5 of the polygon including the inclined line shown in FIG. 5 (a). Layout data after the conversion of the circuit pattern 5 of the polygon including the inclined line shown in FIG. 5A is a polygonal data represented by a plurality of rectangles in a staircase shape and composed entirely of a plurality of rectangles. Although the width | variety R of the rectangle which shows is the range of Rw <R <Rp * m, in FIG.9 (a)-FIG.9 (h), only the shape which the whole consists of several rectangle is shown.
    The layout data shown in Fig. 9A serves as a basis for forming the light shielding pattern 3b shown in Fig. 5B, and the layout data shown in Fig. 9B is shown in Fig. 5C. It is used as a basis for forming the light shielding pattern 3b shown in FIG. 9, and the layout data shown in FIGS. 9C and 9D form the light shielding pattern 3B shown in FIG. 5D. The layout data shown in FIG. 9E serves as a basis for forming the light shielding pattern 3b shown in FIG. 5E, and the layout data shown in FIG. It becomes the basis for forming the light shielding pattern 3b shown to FIG. 5F, The layout data shown to FIG. 9G and FIG. 9H shows the light shielding pattern shown to FIG. 5G. It becomes the basis for forming (3b).
    When the layout data shown in FIG. 9C and the layout data shown in FIG. 9D are compared, the number of rectangles constituting the layout data shown in FIG. 9C and FIG. 9D are shown. The number of rectangles constituting the layout data is the same, and the number of the micro rectangles 9 in the layout data shown in FIG. 9C and the number of the micro rectangles 9 in the layout data shown in FIG. 9D are also the same. However, in the layout data shown in Fig. 9D, a smaller micro rectangle 9 is located in the outer peripheral portion. Therefore, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 9C, the light shielding pattern having a higher precision than that in the case of forming the light shielding pattern based on the layout data shown in FIG. Can be formed. Similarly, in the case where the light shielding pattern is formed based on the layout data shown in FIG. 9H, a light shielding pattern having high precision is formed as compared with the case in which the light shielding pattern is formed based on the layout data shown in FIG. 9G. Can be formed.
    (Example 10)
    10 is a diagram for describing the tenth embodiment. 10A to 10H show layout data after conversion of the circuit pattern 5 of the polygon including the inclined line shown in FIG. 6A. The layout data after conversion of the circuit pattern 5 of the polygon including the inclined line shown in Fig. 6A is a polygonal data represented by a plurality of rectangles in a staircase shape and composed entirely of a plurality of rectangles. Although the width | variety R of the rectangle which shows is the range of Rw <R <Rp * m, in FIG.10 (a)-FIG.10 (h), only the shape which the whole consists of several rectangle is shown.
    The layout data shown in Fig. 10A serves as a basis for forming the light shielding pattern 3b shown in Fig. 6B, and the layout data shown in Fig. 10B is shown in Fig. 6C. It is a basis for forming the light shielding pattern 3b shown in FIG. 10, and the layout data shown in FIGS. 10C and 10D form the light shielding pattern 3B shown in FIG. 6D. The layout data shown in FIG. 10E is the basis for forming the light shielding pattern 3b shown in FIG. 6E, and the layout data shown in FIG. It becomes the basis for forming the light shielding pattern 3b shown to FIG. 6F, The layout data shown to FIG. 10G and FIG. 10H shows the light shielding pattern shown to FIG. It becomes the basis for forming (3b).
    When the layout data shown in Fig. 10G and the layout data shown in Fig. 10H are compared, the number of rectangles constituting the layout data shown in Fig. 10G and Fig. 10H are shown. The number of rectangles constituting the layout data shown is the same, and the number of the micro rectangles 9 in the layout data shown in FIG. 10G and the number of the micro rectangles 9 in the layout data shown in FIG. 10H are also shown. Although the same, the smaller micro rectangle 9 is located in the outer peripheral part in the layout data shown to Fig.10 (h). Therefore, when forming a light shielding pattern based on the layout data shown to Fig.10 (g), the light shielding pattern with high precision compared with the case where a light shielding pattern is formed based on the layout data shown to Fig.10 (h). Can be formed.
    (Example 11)
    In Example 11, the inspection-correction method of the defect which occurred in the photomask demonstrated in Example 1 is demonstrated.
    11 is a view for explaining a method for correcting a defect of a photomask. FIG. 11A shows the state in which the defect 10 is generated at the position of the line 4 corresponding to the inclined line of the light shielding pattern 3b in the photomask 1 described in Example 1, (B) of FIG. 11 has shown the shape after inspection-correction of the defect.
    In general, when a defect occurs in the manufactured photomask, referring to the drawing data, if it is white defect, it is embedded by FIB (Focused Ion Beam), and if it is black defect, it is removed by a laser application and corrected according to the drawing data. For this reason, in the case of inspecting and correcting the defect 10 which occurred in the position of the line 4 corresponded to the inclination line of the light shielding pattern 3b in the photomask 1 demonstrated in Example 1, drawing data is normally Check and correct to step shape by reference.
    However, the shape to be finally formed by using the light shielding pattern 3b in the photomask 1 described in Embodiment 1 is a shape of a polygon including an oblique line, that is, a circuit pattern. For this reason, even if the defect 10 which generate | occur | produced in the position of the line 4 corresponded to the inclination line of the light shielding pattern 3b is checked and corrected diagonally with reference to the layout data of a circuit pattern, there is no inconvenience.
    As described above, according to the eleventh embodiment, when the defect 10 generated at the position of the line 4 corresponding to the inclined line of the light shielding pattern 3b is inspected and corrected at an angle with reference to the layout data of the circuit pattern, Since there is no need to inspect and correct the steps, the effect of easily inspecting and correcting the defect 10 can be obtained.
    (Example 12)
    In Example 12, the method of using the photomask described in Example 1 will be described.
    12 is a diagram for describing a method of using a photomask. FIG. 12A shows the projection exposure apparatus 201, FIG. 12B shows the photomask 1 described in Embodiment 1 mounted on the projection exposure apparatus 201, and FIG. 12C. Indicates a wafer 11 exposed by the projection exposure apparatus 201.
    The light shielding pattern 3b shows a circuit pattern of a polygon including an inclined line as a polygon in which the inclined line is represented in a step shape by a plurality of rectangles, and the height of one step of the stairs, that is, the width of the rectangle representing the inclined line ( R) is in the range of Rw <R <Rp · m. For this reason, when the wafer 11 is exposed using the photomask 1 described in Example 1, the shape of the light shielding pattern 3b cannot be accurately transferred, and the stepped shape is transferred as an oblique line, and the wafer ( 11, a light shielding pattern 12 having a circuit pattern shape is formed.
    Therefore, when manufacturing a semiconductor integrated circuit or a liquid crystal display using the photomask 1 demonstrated in Example 1, a highly reliable semiconductor integrated circuit or a liquid crystal display can be manufactured.
    As described above, according to the present invention, the transparent substrate and the circuit pattern of the polygon including the inclined line are provided with a light shielding pattern in which the inclined line is represented as a polygon represented by a plurality of rectangles in a stepped shape. ), The photomask is constructed so that Rw < R < Rp · m (where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus). There is an effect of obtaining a photomask.
    According to the present invention, when the photomask is configured such that the area of the polygon including the inclined line is equal to the area of the polygon shown in the step shape, the circuit pattern is mounted on the wafer when the wafer is exposed by mounting the exposure apparatus. It is possible to obtain a photomask capable of transferring the film with high accuracy.
    According to the present invention, the side connected to the end of the inclined line in the polygon including the inclined line and the side connected to the position corresponding to the end of the inclined line in the polygon in which the inclined line is stepped are in parallel relationship. When the mask is configured, a photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, a photo is connected so that the side connecting to the end of the inclined line in the polygon including the inclined line and the side connecting to the position corresponding to the end of the inclined line in the polygon represented by the step shape are in a right angle relationship. When the mask is configured, a photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are parallel to each other, the photomask is arranged such that the stepped shape representing the inclined line becomes point symmetric with respect to the midpoint of the line corresponding to the inclined line. When configured, the photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are parallel to each other, the stepped shape indicating the inclined line is mirror-symmetric with respect to the vertical bisector of the line corresponding to the inclined line. When the mask is configured, a photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are perpendicular to each other, the photomask is formed such that the stepped shape representing the inclined line becomes point symmetric with respect to the midpoint of the line corresponding to the inclined line. When configured, the photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, when the sides connected to the ends of the inclined line in the polygon including the inclined line are perpendicular to each other, the stepped shape representing the inclined line is mirror symmetric with respect to the vertical bisector of the line corresponding to the inclined line, When the photomask is formed, a photomask capable of transferring the circuit pattern on the wafer with high accuracy when mounted on the exposure apparatus and exposing the wafer can be obtained.
    According to the present invention, a process of laying out a circuit pattern, creating the layout data, and layout data of a polygonal circuit pattern including an inclined line, wherein the inclined line is represented in steps by a plurality of rectangles, and a plurality of the whole are arranged. A process of converting the polygonal data consisting of a rectangular rectangle and a process of drawing the circuit pattern on the basis of the layout data after the conversion of the circuit pattern of the polygon including the oblique lines, and the layout of the polygonal circuit patterns including the oblique lines In the process of converting data, the width R of the rectangle representing the oblique line is in the range of Rw < R < Rp · m, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is Resolution of Mask Drawing Apparatus) Since the photomask manufacturing method is constructed, a highly accurate photomask can be manufactured at low cost. There are effective.
    According to the present invention, when there are a plurality of methods for converting layout data of a polygonal circuit pattern including an oblique line, if the photomask manufacturing method is configured to select a method in which the total number of rectangles is small, the amount of data after conversion There is less effect.
    According to the present invention, when there are a plurality of methods for converting layout data of a polygonal circuit pattern including an inclined line, the method of manufacturing the photomask is selected so that the method with a small number of micro rectangles is selected. There is an effect that can produce a photomask.
    According to the present invention, when there are a plurality of methods for converting layout data of a circuit pattern of a polygon including an inclined line, a method of manufacturing a photomask is selected so that a method in which the micro rectangle is not located at the outer periphery of the polygon consisting of a plurality of rectangles is selected. When comprised, there exists an effect which can manufacture the photomask which has a high light shielding pattern.
    According to the present invention, a transparent substrate and a circuit pattern of a polygon including an oblique line are provided with a light shielding pattern in which the oblique line is represented as a polygon represented by a plurality of rectangles in a stepped shape, and the width of the rectangle R is Rw. When inspecting and correcting a defect occurring at a position of a line corresponding to an inclination line of the photomask in a range of <R <Rp · m, inspecting and correcting it at an angle with reference to the layout data of the circuit pattern (where m denotes the transfer magnification of the exposure apparatus, Since Rp is the resolution of the exposure apparatus and Rw is the resolution of the mask drawing apparatus), the inspection and correction method for the photomask is constituted, so that inspection and correction of defects occurring at the position of the line corresponding to the oblique line can be easily performed.
    According to the present invention, a transparent substrate and a circuit pattern of a polygon including an inclined line are provided with a light shielding pattern in which the inclined line is represented as a polygon represented by a plurality of rectangles, and the width of the rectangle is Rw. Using a photomask in the range of <R <Rp · m, m is a transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus. Since the use method is configured, there is an effect that a semiconductor integrated circuit with high reliability can be manufactured at low cost.
    According to the present invention, there is provided a light shielding pattern in which a transparent circuit board and a polygonal circuit pattern including an inclined line are represented as polygons represented in a step shape by a plurality of rectangles, and the width of the rectangle R is Rw <R < Using a photomask in the range of Rp · m, a liquid crystal display is manufactured (where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus). As a result, the semiconductor integrated circuit can be manufactured at low cost and with high reliability.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] With a transparent substrate,
    A circuit pattern of a polygon including an inclination line and having a light shielding pattern in which the inclination line is represented as a polygon represented by a plurality of rectangles in a step shape,
    A photomask in which the width R of the rectangle is in the range of Rw < R < Rpm, where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus. .
    [2" claim-type="Currently amended] Laying out the circuit pattern and creating the layout data;
    Converting layout data of a circuit pattern of a polygon including an inclined line into polygonal data in which the inclined line is represented in a step shape by a plurality of rectangles, and the whole consists of a plurality of rectangles;
    Comprising a step of drawing a circuit pattern based on the layout data after the conversion of the circuit pattern of the polygon including the oblique line,
    In the step of converting the layout data of the polygonal circuit pattern including the inclined line, the width R of the rectangle representing the inclined line is in the range of Rw <R <Rp · m. Where m is the transfer magnification of the exposure apparatus, Rp is the resolution of the exposure apparatus, and Rw is the resolution of the mask drawing apparatus.
    [3" claim-type="Currently amended] A light shielding pattern having a transparent substrate and a polygonal circuit pattern including an inclined line, wherein the inclined line is represented as a polygon represented by a plurality of rectangles in a stepped shape,
    Inspecting and correcting a defect occurring at a position of a line corresponding to the inclined line of the photomask in which the width R of the rectangle is in the range of Rw <R <Rp · m, checks and checks at an angle with reference to the layout data of the circuit pattern. (A) m is a transfer magnification of the exposure apparatus, Rp is a resolution of the exposure apparatus, and Rw is a resolution of the mask drawing apparatus.
    [4" claim-type="Currently amended] A light shielding pattern having a transparent substrate and a circuit pattern of a polygon including an inclination line, wherein the inclination line is represented as a polygon in a stepped shape by a plurality of rectangles,
    A method of using a photomask for manufacturing a semiconductor integrated circuit using a photomask in which the width R of the rectangle is in the range of Rw <R <Rp · m, provided that m is a transfer magnification of an exposure apparatus and Rp is an exposure. Resolution of the device, Rw is the resolution of the mask drawing device).
    [5" claim-type="Currently amended] A transparent substrate and a circuit pattern of a polygon including an inclination line, and a light shielding pattern in which the inclination line is represented as a polygon represented by a step shape by a plurality of rectangles,
    A method of using a photomask for producing a liquid crystal display using a photomask in which the width R of the rectangle is in the range of Rw < R < Rp · m, wherein m is the transfer magnification of the exposure apparatus, and Rp is the Resolution, Rw is the resolution of the mask drawing device).
    类似技术:
    公开号 | 公开日 | 专利标题
    JP6342436B2|2018-06-13|Method and apparatus for analyzing and removing defects in EUV photomasks
    US10107621B2|2018-10-23|Image based overlay measurement with finite gratings
    JP5821100B2|2015-11-24|Method and apparatus for correcting errors on a wafer processed by a photolithographic mask
    TWI512413B|2015-12-11|System for lithography alignment
    KR100733546B1|2007-06-28|Method and System for Selective Linewidth Optimization During a Lithographic Process
    US6667486B2|2003-12-23|Electron beam exposure method, electron beam exposure apparatus and device manufacturing method using the same
    JP4098502B2|2008-06-11|Mask manufacturing method and LSI manufacturing method
    US7454051B2|2008-11-18|Method of manufacturing photo mask, mask pattern shape evaluation apparatus, method of judging photo mask defect corrected portion, photo mask defect corrected portion judgment apparatus, and method of manufacturing a semiconductor device
    JP4218528B2|2009-02-04|Method for forming exposure mask pattern and method for manufacturing semiconductor device
    US7468240B2|2008-12-23|Patterning method using photomask
    KR101540215B1|2015-07-29|Evaluation method of inspection sensitivity
    KR100776479B1|2007-11-16|Writing method and writing apparatus of charged particle beam and positional deviation measuring method and position measuring apparatus
    JP3977302B2|2007-09-19|Exposure apparatus, method of using the same, and device manufacturing method
    TW563042B|2003-11-21|Overlay error mode, its sampling strategy procedure and device using the mode and strategy procedure
    US7615746B2|2009-11-10|Method and apparatus for evaluating pattern shape of a semiconductor device
    JP4494221B2|2010-06-30|Photomask, manufacturing method thereof, and pattern forming method
    JP5695924B2|2015-04-08|Defect estimation apparatus, defect estimation method, inspection apparatus, and inspection method
    KR101257961B1|2013-04-24|Overlay measurement target
    KR100528109B1|2005-11-15|Method of correcting proximity effect of electronic beam exposure, exposure method, manufacturing method of semiconductor device, and proximity effect correction module
    US6245584B1|2001-06-12|Method for detecting adjustment error in photolithographic stepping printer
    US7678516B2|2010-03-16|Test structures and methods for monitoring or controlling a semiconductor fabrication process
    US7594216B2|2009-09-22|Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask
    KR100845347B1|2008-07-09|Composite patterning with trenches
    US5087537A|1992-02-11|Lithography imaging tool and related photolithographic processes
    KR100572940B1|2006-04-25|Monitoring method, exposure method, method of manufacturing semoconductor device, etching method and exposure processing apparatus
    同族专利:
    公开号 | 公开日
    DE10002316A1|2000-09-07|
    US6228542B1|2001-05-08|
    JP2000241958A|2000-09-08|
    JP4756720B2|2011-08-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-02-19|Priority to JP99-042230
    1999-02-19|Priority to JP04223099A
    2000-01-28|Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤
    2000-09-25|Publication of KR20000057825A
    2002-05-10|Application granted
    2002-05-10|Publication of KR100336031B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP99-042230|1999-02-19|
    JP04223099A|JP4756720B2|1999-02-19|1999-02-19|Photomask, photomask manufacturing method, photomask inspection correction method, semiconductor integrated circuit manufacturing method, and liquid crystal display manufacturing method|
    [返回顶部]